1. Field of the Invention
The present invention relates to the field of integrated circuits and, more particularly, to an apparatus and method of forming a DRAM cell array with a reduced overall stack height and better alignment tolerance between DRAM container cells and bit line contacts.
2. Description of the Related Art
Modern integrated circuit designers often must confront and solve the problem of space limitations on the circuit die. Because the use and popularity of memory devices, such as dynamic random access memory (DRAM) circuits, has expanded dramatically in recent years, memory circuit manufacturers have been under pressure to increase memory capacity and performance without increasing the space occupied by the circuit.
For example, DRAM memory circuits are manufactured by replicating millions of identical circuit elements, known as DRAM cells, on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a storage capacitor and an access field effect transistor.
FIG. 10 illustrates a portion of a DRAM memory circuit containing two neighboring DRAM cells 100. For each cell, one plate of the storage capacitor 140 is connected to a reference voltage and the other plate is connected to the drain of the access field effect transistor 120. The gate of the access field effect transistor 120 is connected to the word line 180. The source of the field effect transistor 120 is connected to the bit line 160. The word line thus controls access to the storage capacitor 140 by allowing or preventing the logic signal (xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) on the bit line 160 to be written to or read from the storage capacitor 140.
The manufacturing of a DRAM cell includes the fabrication of a transistor, a capacitor, and contacts to the bit line, the word line, and the reference voltage. DRAM manufacturing is a highly competitive business. There is continuous pressure to decrease the size of individual cells and increase memory cell density to allow more memory to be squeezed onto a single memory chip. However, it is necessary to maintain a sufficiently high storage capacitance to maintain a charge at the refresh rates currently in use even as cell size continues to shrink. This requirement has led DRAM manufacturers to turn to three dimensional capacitor designs, including stacked capacitors. Stacked capacitors are capacitors which are stacked, or placed, over the access transistor in a semiconductor device. For reasons including ease of fabrication and increased capacitance, most manufacturers of DRAMs larger than 4 Megabits use stacked capacitors. Therefore, the invention will be discussed in connection with stacked capacitors but should not be understood to be limited thereto. For example, use of the invention in trench or planar capacitors is also possible.
One widely used type of stacked capacitor is known as a container capacitor, shown in FIG. 11. One embodiment of a container capacitor is shaped like an upstanding tube (cylinder) having an oval or circular cross section. FIG. 11 illustrates a top view of a portion of a DRAM memory circuit from which the upper layers have been removed to reveal container capacitors 114 arranged around a bit line contact 62. Six container capacitors are shown in FIG. 11, each of which has been labeled with separate reference designations A to F.
To increase density, the bit line contact 62 is shared by neighboring container capacitors 114, including those labeled A and B. The wall of each container capacitor consists of two plates 82, 94 of conductive material such as doped polycrystalline silicon (referred to herein as polysilicon or poly) separated by a dielectric layer 92. The bottom end of the tube is closed, with the inner wall (lower plate 82) in contact with either the drain of the access transistor or a plug which itself is in contact with the drain. The other end of the tube is open (the tube is filled with an insulative material 102 later in the fabrication process). The sidewall and closed end of the tube form a container; hence the name xe2x80x9ccontainer capacitorxe2x80x9d.
The container capacitors in FIG. 11 are double-sided, meaning the lower plate 82 is surrounded on two sides by the upper plate 94, which is connected to a reference voltage on the periphery (not shown). The use of double-sided capacitors further increases the storage capacitance of the DRAM memory cell, reducing the required depth of the container, but their use requires more lateral space for the second side of the upper plate. Lateral space is at a premium due to the need to increase circuit density while preserving isolation of the capacitor plates from the bit line contact. It would be desirable to develop a technique which improves alignment tolerance of the bit line contacts so that double-sided container capacitors could be squeezed closer together.
Additional space savings on the circuit die are required in order to satisfy the demand on DRAM manufacturers for increased capacity memory circuits. In order to remain competitive, DRAM manufacturers need a circuit design that conserves space on the circuit die but does not require unusually expensive or unconventional processing techniques. Therefore, there is a strong need for an increased-density stacked capacitor memory array design exhibiting improved alignment tolerance, utilizing three-dimensional double-sided capacitors and capable of formation by conventional wafer processing and manufacturing techniques.
The present invention provides an apparatus and method of forming a DRAM memory cell array exhibiting improved alignment tolerance for bit line contact formation and utilizing closely-spaced double-sided stacked capacitors for increased overall feature density on the circuit die.
The above and other features and advantages of the invention are achieved by providing an apparatus and associated method of forming a semiconductor device including:
(a) forming an insulating layer on a semiconductor assembly composed of a plurality of gates and a plurality of conductive plugs formed between the gates;
(b) etching a plurality of holes or contact openings in the insulating layer to expose only selected plugs (xe2x80x98bit-line plugsxe2x80x99);
(c) forming insulating spacers on the sidewalls of the contact openings;
(d) forming conductive bit line contact plugs in the contact openings between the insulating spacers;
(e) etching additional contact openings in the insulating layer laterally adjacent the bit line contact plugs and forming double-sided capacitors in the additional contact openings, removing the remainder of the insulating layer with wet etch techniques during capacitor formation; and
(f) forming a conductive bit line in contact with the bit line contact plugs.
In the present invention, the use of insulating spacers surrounding the bit line contact plug, and a wet etch that selectively stops at those spacers, permits the double-sided capacitors to be formed close together. Only the previously-formed bit line plug and insulating sidewall spacers separates adjacent capacitors from the bit line contact and hence DRAM cells can be more tightly packed on the circuit die.
Another aspect of the invention is improved alignment tolerance of the bit line contact plug. Because the bit line contact plug is formed prior to the double-sided capacitors, and then the double sided capacitors are formed to occupy all of the space laterally surrounding the bit line contact plug and its insulating spacers, mask alignment errors that plagued prior art devices (with after-formed bit line contact plugs) are less likely to affect this arrangement.
The apparatus of the invention includes a plurality of gates and a plurality of closely-spaced container capacitors formed above contact plugs formed between the gates. The container capacitors are separated by a bit line contact plug and an insulating spacer surrounding the plug. The apparatus is formed to permit close spacing of the container capacitors relative to each other, wherein only an insulating spacer separates the contact plug from a container capacitor on either side of the plug.
Furthermore, the present invention provides these and other advantages solely using processing techniques conventionally employed in the manufacture of semiconductor devices. No unusually expensive or cumbersome steps are required in the method of the present invention, resulting in improved device performance without substantially increased cost.